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Dr. CU · Issue #3535 · YosysHQ/yosys · GitHub

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functions returning void not supported · Issue #3231 · YosysHQ/yosys ...

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Support set_dont_use · Issue #3638 · YosysHQ/yosys · GitHub

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Write to the same memory in different always blocks · Issue #3750 ...

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Support System Verilog Labeled Statements Issue 538 Yosyshq Yosys - Best Space Backgrounds in Retina
Wrong output when converting Verilog to AIG · Issue #350 · YosysHQ ...

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Support System Verilog Labeled Statements Issue 538 Yosyshq Yosys - Best Space Designs in Retina
SystemVerilog var port kind · Issue #987 · YosysHQ/yosys · GitHub

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Equivalence Check Issue · Issue #302 · YosysHQ/yosys · GitHub

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convert verilog to aiger with Yosys · Issue #2850 · YosysHQ/yosys · GitHub

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